8-bit NAND
%%verilog
// definition of 1-bit nand gate [3]
module NAND_gate (
input I0,
input I1,
output O0
);
// logic for nand gate
assign O0 = ~(I0 & I1);
endmodule
// 8-bit NAND gate using eight 1-bit NAND gates [3]
module nand_gate_8bit (
input [7:0] NAND_in_a,
input [7:0] NAND_in_b,
output [7:0] NAND_out
);
// instantiation of eight 1-bit NAND gates
NAND_gate inst1(NAND_in_a[0], NAND_in_b[0], NAND_out[0]);
NAND_gate inst2(NAND_in_a[1], NAND_in_b[1], NAND_out[1]);
NAND_gate inst3(NAND_in_a[2], NAND_in_b[2], NAND_out[2]);
NAND_gate inst4(NAND_in_a[3], NAND_in_b[3], NAND_out[3]);
NAND_gate inst5(NAND_in_a[4], NAND_in_b[4], NAND_out[4]);
NAND_gate inst6(NAND_in_a[5], NAND_in_b[5], NAND_out[5]);
NAND_gate inst7(NAND_in_a[6], NAND_in_b[6], NAND_out[6]);
NAND_gate inst8(NAND_in_a[7], NAND_in_b[7], NAND_out[7]);
endmodule
// test bench for nand gate [3]
module nand_tb();
// input signals
reg [7:0] NAND_in_a, NAND_in_b;
// output signals
wire [7:0] NAND_out;
nand_gate_8bit INST(NAND_in_a, NAND_in_b, NAND_out);
// block for test bench
initial begin
$display("nand test bench");
#10 NAND_in_a=8'b0000001; NAND_in_b=8'b0000001;
#10 $monitor("%b NAND %b = %b", NAND_in_a,NAND_in_b,NAND_out);
#10 NAND_in_a=8'b00011111; NAND_in_b=8'b00110011;
$finish;
end
endmodule
8-BIT OR-GATE
%%verilog
// or gate - quiñones
module OR_gate (
input I0,
input I1,
output O0
);
assign O0 = I0 | I1;
endmodule
module or_gate_8bit (
input [7:0] OR_in_a,
input [7:0] OR_in_b,
output [7:0] OR_out
);
OR_gate inst1(OR_in_a[0], OR_in_b[0], OR_out[0]);
OR_gate inst2(OR_in_a[1], OR_in_b[1], OR_out[1]);
OR_gate inst3(OR_in_a[2], OR_in_b[2], OR_out[2]);
OR_gate inst4(OR_in_a[3], OR_in_b[3], OR_out[3]);
OR_gate inst5(OR_in_a[4], OR_in_b[4], OR_out[4]);
OR_gate inst6(OR_in_a[5], OR_in_b[5], OR_out[5]);
OR_gate inst7(OR_in_a[6], OR_in_b[6], OR_out[6]);
OR_gate inst8(OR_in_a[7], OR_in_b[7], OR_out[7]);
endmodule
module or_tb();
reg [7:0] OR_in_a, OR_in_b;
wire [7:0] OR_out;
or_gate_8bit INST(OR_in_a, OR_in_b, OR_out);
initial begin
$display("or test bench");
#10 OR_in_a=8'b10000000; OR_in_b=8'b00000001;
#10 $monitor("%b OR %b = %b", OR_in_a, OR_in_b, OR_out);
#10 OR_in_a=8'b00011111; OR_in_b=8'b00110011;
$finish;
end
endmodule
8-BIT XOR-GATE
%%verilog
// definition of 1-bit xor gate [3]
module XOR_gate (
input I0,
input I1,
output O0
);
// logic for xor gate
assign O0 = I0 ^ I1;
endmodule
// definition of 8-bit xor gate using 1-bit xor gates [3]
module xor_gate_8bit (
input [7:0] XOR_in_a,
input [7:0] XOR_in_b,
output [7:0] XOR_out
);
// instantiation
XOR_gate inst1(XOR_in_a[0], XOR_in_b[0], XOR_out[0]);
XOR_gate inst2(XOR_in_a[1], XOR_in_b[1], XOR_out[1]);
XOR_gate inst3(XOR_in_a[2], XOR_in_b[2], XOR_out[2]);
XOR_gate inst4(XOR_in_a[3], XOR_in_b[3], XOR_out[3]);
XOR_gate inst5(XOR_in_a[4], XOR_in_b[4], XOR_out[4]);
XOR_gate inst6(XOR_in_a[5], XOR_in_b[5], XOR_out[5]);
XOR_gate inst7(XOR_in_a[6], XOR_in_b[6], XOR_out[6]);
XOR_gate inst8(XOR_in_a[7], XOR_in_b[7], XOR_out[7]);
endmodule
// test bench for xor gate [3]
module xor_tb();
// input signals
reg [7:0] XOR_in_a, XOR_in_b;
// output signals
wire [7:0] XOR_out;
xor_gate_8bit INST(XOR_in_a, XOR_in_b, XOR_out);
initial begin
$display("xor test bench");
#10 XOR_in_a=8'b0000001; XOR_in_b=8'b0000001;
#10 $monitor("%b XOR %b = %b", XOR_in_a,XOR_in_b,XOR_out);
#10 XOR_in_a=8'b00011111; XOR_in_b=8'b00110011;
$finish;
end
endmodule
PROJ-FUNC
%%verilog
// definition of 1-bit OR gate
module OR_gate (
input I0,
input I1,
output O0
);
// logic for OR
assign O0 = I0 | I1;
endmodule
// definition of 8-bit OR gate
module or_gate_8bit (
input [7:0] OR_in_a,
input [7:0] OR_in_b,
output [7:0] OR_out
);
// instantiation of eight 1-bit OR gates
OR_gate inst1(OR_in_a[0], OR_in_b[0], OR_out[0]);
OR_gate inst2(OR_in_a[1], OR_in_b[1], OR_out[1]);
OR_gate inst3(OR_in_a[2], OR_in_b[2], OR_out[2]);
OR_gate inst4(OR_in_a[3], OR_in_b[3], OR_out[3]);
OR_gate inst5(OR_in_a[4], OR_in_b[4], OR_out[4]);
OR_gate inst6(OR_in_a[5], OR_in_b[5], OR_out[5]);
OR_gate inst7(OR_in_a[6], OR_in_b[6], OR_out[6]);
OR_gate inst8(OR_in_a[7], OR_in_b[7], OR_out[7]);
endmodule
// definition of 1-bit sub [3]
module subtract1(
input a_bit, b_bit,
input cin_bit,
output sum_bit,
output cout_bit
);
// logic for 1-bit subtraction
assign sum_bit = (a_bit ^ b_bit) ^ cin_bit;
assign cout_bit = (~a_bit & b_bit) | (~(a_bit ^ b_bit) & cin_bit);
endmodule
// definition of 8-bit sub [3]
module subtract_8bits(
input [7:0] a,
input [7:0] b,
output [7:0] result
);
wire [7:0] borrow;
// instantiation of eight 1-bit subtractors
subtract1 sub[7:0] (
.a_bit(a[0]),
.b_bit(b[0]),
.cin_bit(1'b0),
.sum_bit(result[0]),
.cout_bit(borrow[0])
);
// generate block for loop instantiation
generate
genvar i;
for (i = 1; i < 8; i = i + 1) begin : sub_gen
subtract1 sub_i (
.a_bit(a[i]),
.b_bit(b[i]),
.cin_bit(borrow[i-1]),
.sum_bit(result[i]),
.cout_bit(borrow[i])
);
end
endgenerate
endmodule
// function combining OR and subtract operations
module proj_func(
input [7:0] func_in_a,
input [7:0] func_in_b,
output [7:0] func_out
);
wire [0:7] OR_out;
// or gate
or_gate_8bit inst1(
.OR_in_a(func_in_a),
.OR_in_b(func_in_b),
.OR_out(OR_out)
);
// subtractor
subtract_8bits inst2 (
.a(OR_out),
.b(func_in_b),
.result(func_out)
);
endmodule
// test bench for function
module function_tb;
reg [7:0] a;
reg [7:0] b;
wire [7:0] out;
proj_func f7(a,b,out);
initial begin
a = 8'b10000000; b=8'b00000001;
#10 $display("out = %b", out);
$finish;
end
endmodule
